Person: HAMZAOĞLU, Ilker
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Ilker
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HAMZAOĞLU
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ArticlePublication Open Access An efficient versatile video coding motion estimation hardware(Springer, 2024-04) Ahmad, W.; Mahdavi, H.; Hamzaoğlu, İlker; Computer Science; HAMZAOĞLU, IlkerVersatile Video Coding (VVC) is the latest video coding standard. It provides higher compression efficiency than the previous video coding standards at the cost of significant increase in computational complexity. Motion estimation (ME) is the most time consuming and memory intensive module in VVC encoder. Therefore, in this paper, we propose an efficient VVC ME hardware. It is the first VVC ME hardware in the literature. It has real time performance with small hardware area. This efficiency is achieved by using a 64 × 64 systolic processing element array to support maximum coding tree unit (CTU) size of 128 × 128 and by using a novel memory-based sum of absolute differences (SAD) adder tree to calculate SADs of 128 × 128 CTUs. The proposed VVC ME hardware reduces memory accesses significantly by using an efficient data reuse method. It can process up to 30 4 K (3840 × 2160) video frames per second.ArticlePublication Metadata only An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture(Elsevier, 2023-11) Ghanim, Mustafa; Tasdizen, O.; Uğurdağ, Hasan Fatih; Hamzaoğlu, İlker; Electrical & Electronics Engineering; Computer Science; UĞURDAĞ, Hasan Fatih; HAMZAOĞLU, Ilker; Ghanim, MustafaThis paper proposes a low-cost disparity map compression algorithm and its hardware architecture for high resolution and high frame rate applications. The proposed algorithm uses spatial correlations between neighboring disparities and has two variants. The first variant encodes the current disparity using its left neighbor, whereas the second variant benefits from left and upper neighbors. The proposed algorithm obtains 48% and 56% savings in memory space on the average for its variants. The proposed architecture can support 1080p resolution at 60 fps on a low-cost FPGA device while consuming very low area and power.