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Now showing items 11-20 of 32
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration
(Elsevier, 2013-02)
This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. ...
RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
Generating fast logic circuits for m-select n-port round Robin arbitration
(IEEE, 2013)
This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ...
Design and simulation of an optimal energy management strategy for plug-In electric vehicles
(IEEE, 2018)
Energy management algorithms play a critical role in improving the energy efficiency of modern electric vehicles. In order to be desirable for the customer, electric vehicles should be capable of long distance driving on ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
Output domain downscaler
(ISCIS 2016: Computer and Information Sciences, 2016)
This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ...
Preface
(Springer Science+Business Media, 2015)
Software defined VLC system: implementation and performance evaluation
(IEEE, 2015)
This paper presents the implementation of an IEEE standard-based Visible Light Communication (VLC) system using software defined radio (SDR) approach. Based on widely used SDR platform Universal Software Radio Peripheral ...
FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication
(IEEE, 2020-09)
A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to ...
Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01)
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques ...
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