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Enabling difference-based dynamic partial self reconfiguration for large differences
(IEEE, 2013)
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ...
FPGA bitstream protection with PUFs, obfuscation, and multi-boot
(IEEE, 2011)
With the combination of PUFs, obfuscation, and multi-boot, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have ...
Cost-benefit approach to degradation of electrolytic capacitors
(IEEE, 2014)
Aluminum electrolytic capacitors are widely used as a filter or bulky capacitor after rectification stages of switching power supplies (SMPS). Fly-back, forward, and resonant converter topologies, which are widely used in ...
Synthesis of clock trees for sampled-data analog IC blocks
(IEEE, 2013)
This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which ...
Combined AES + AEGIS architectures for high performance and lightweight security applications
(Springer International Publishing, 2014)
AES has been the prominent block cipher since its introduction as the standard. It has been the cipher used in almost all new applications that require solid, unbreakable security with reasonable resource usage. Several ...
CPU design simplified
(IEEE, 2018-12-10)
The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ...
Defect-aware nanocrossbar logic mapping through matrix canonization using two-dimensional radix sort
(ACM, 2011-08)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ...
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
(IEEE, 2019)
As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the ...
A multi-channel real time implementation of dual tree complex wavelet Transform in field programmable gate arrays
(Springer International Publishing, 2016)
In medical applications, biomedical acquisition systems (BASs) are frequently used in order to diagnose and monitor critical conditions such as stroke, epilepsy, Alzheimer disease, arrhythmias and etc. Biomedical signals ...
Fast one- and two-pick fixed-priority selection and muxing circuits
(IEEE, 2016)
Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with ...
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