Search
Now showing items 11-19 of 19
Efficient combinational circuits for division by small integer constants
(IEEE, 2016)
Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of ...
Using high-level synthesis for rapid design of video processing pipes
(IEEE, 2016)
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the ...
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays
(IEEE, 2015)
Biomedical signals (BSs), which give information about the normal condition and also the inherent irregularities of our body, are expected to have non-stationary character due to the time-varying behavior of physiological ...
Referanssız görüntü bloklanma ölçümü için yeni bir yöntem
(IEEE, 2014)
Internet’te ve servis sağlayıcı ağlarında video trafiğinin tavan yaptığı günümüzde otomatik görüntü kalitesi ölçümünün faydaları aşikardır. Bu ölçümlerin birçok uygulamada gerçekzamanlı yapılması gerekir ve de bu “Referanssız” ...
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
(Springer International Publishing, 2017)
FPGA acceleration of compute-intensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Data-parallel algorithms have an alternative platform for acceleration, ...
Welcome from the general chairs
(IEEE, 2013)
A fast circuit topology for finding the maximum of n k-bit numbers
(IEEE, 2013)
Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) ...
Darbe i̇şaretleri̇ i̇çi̇n aşırı-hızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
(IEEE, 2012)
Bu çalışmada anlatılan donanım 1.5 GHz Analog-Sayısal- Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ...
Software UART: A use case for VSCPU worst-case execution time analyzer
(IEEE, 2019)
This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken ...
Share this page