Enabling difference-based dynamic partial self reconfiguration for large differences
Type :
Conference paper
Publication Status :
published
Access :
restrictedAccess
Abstract
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.
Source :
2013 8th IEEE Design and Test Symposium
Date :
2013
Publisher :
IEEE
URI
http://hdl.handle.net/10679/2346http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6727108
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