A 1GS/s, 9-bits DAC interleaved (2+1)-bit then 2-bit per cycle SAR ADC

Abstract

This paper presents a high speed Successive Approximation Register Analog to Digital Converter (SAR ADC) for low-noise low-power satellite transceiver applications. The system is a (2+1) then 2-bit per cycle SAR ADC of 1GS/s sampling rate, 9-bits resolution designed in a 65nm standard CMOS technology. The system resolves 9 bits with a special switching scheme in a total of 4 cycles per sample. This is achieved by interleaving 4 Capacitive Digital to Analog Converter (C-DACs) of unit capacitance 1fF. Since the interleaving is limited to the DACs only which match well, the design does not suffer from the drawbacks of full interleaving. Hence, better power efficiency and performance metrics were obtained in comparison to regular interleaved ADCs. A special timing with an extra first bit comparator is optimized to leave proper timing margins for every step from a single 4-GHz low noise clock source which is readily available in the 8- GHz direct conversion front-end. This comparator is reused as all the other active comparators in the both interleaving phases. The proposed design achieved an effective number of bits (ENOB) of 8.2 bits at Nyquist with power consumption of 12mW, resulting in a Figure of Merit (FoM) of 38.37 fJ/conversion-step.