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Generating fast logic circuits for m-select n-port round Robin arbitration

dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorTemizkan, F.
dc.contributor.authorGören, S.
dc.contributor.departmentElectrical & Electronics Engineering
dc.contributor.ozuauthorUĞURDAĞ, Hasan Fatih
dc.date.accessioned2014-11-24T11:09:02Z
dc.date.available2014-11-24T11:09:02Z
dc.date.issued2013
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.en_US
dc.description.abstractThis paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our solutions, however, are based on parallel prefix networks, where the nodes are replaced by "saturated adder"s. We use mPE as a building block to construct an mRRA, which has single cycle latency and can arbitrate up to m requests per clock cycle. We took two arbiters from the liter rature, TC-PPA (1-select) and 3DP2S (2-select), and generalized them into mRRAs, which we call mTC-PPA and 3DPmS-RRA. We wrote fully parameterized HDL code generators. Logic synthesis results show that mTC-PPA and 3DPmS-RRA are up to 100% faster than the cascade solution and have up to 65% smaller Area-Timing Products (ATP). Comparing mTC-PPA and 3DPmS-RRA, 3DPmS-RRA circuits are slightly faster than mTC-PPA on the average. In terms of ATP, mTC-PPA is superior by far and can be as small as 30% of 3DPmS-RRA.en_US
dc.identifier.doi10.1109/VLSI-SoC.2013.6673286
dc.identifier.endpage265
dc.identifier.isbn978-1-4799-0524-9
dc.identifier.scopus2-s2.0-84899549514
dc.identifier.startpage260
dc.identifier.urihttp://hdl.handle.net/10679/664
dc.identifier.urihttps://doi.org/10.1109/VLSI-SoC.2013.6673286
dc.identifier.wos000332046100051
dc.language.isoengen_US
dc.peerreviewedyesen_US
dc.publicationstatuspublisheden_US
dc.publisherIEEEen_US
dc.relation.ispartof2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
dc.relation.publicationcategoryInternational
dc.rightsrestrictedAccess
dc.subject.keywordsAddersen_US
dc.subject.keywordsLogic circuitsen_US
dc.titleGenerating fast logic circuits for m-select n-port round Robin arbitrationen_US
dc.typeconferenceObjecten_US
dc.type.subtypeConference paper
dspace.entity.typePublication
relation.isOrgUnitOfPublication7b58c5c4-dccc-40a3-aaf2-9b209113b763
relation.isOrgUnitOfPublication.latestForDiscovery7b58c5c4-dccc-40a3-aaf2-9b209113b763

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