Publication: Generating fast logic circuits for m-select n-port round Robin arbitration
dc.contributor.author | Uğurdağ, Hasan Fatih | |
dc.contributor.author | Temizkan, F. | |
dc.contributor.author | Gören, S. | |
dc.contributor.department | Electrical & Electronics Engineering | |
dc.contributor.ozuauthor | UĞURDAĞ, Hasan Fatih | |
dc.date.accessioned | 2014-11-24T11:09:02Z | |
dc.date.available | 2014-11-24T11:09:02Z | |
dc.date.issued | 2013 | |
dc.description | Due to copyright restrictions, the access to the full text of this article is only available via subscription. | en_US |
dc.description.abstract | This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high throughput buses. We first propose fast/novel circuits for the fundamental problem of finding the first m 1's in an n-bit vector (from the left or right), i.e., generalized select Priority Encoder (mPE). The obvious solution to mPE is cascading m regular (1-select) PEs. Our solutions, however, are based on parallel prefix networks, where the nodes are replaced by "saturated adder"s. We use mPE as a building block to construct an mRRA, which has single cycle latency and can arbitrate up to m requests per clock cycle. We took two arbiters from the liter rature, TC-PPA (1-select) and 3DP2S (2-select), and generalized them into mRRAs, which we call mTC-PPA and 3DPmS-RRA. We wrote fully parameterized HDL code generators. Logic synthesis results show that mTC-PPA and 3DPmS-RRA are up to 100% faster than the cascade solution and have up to 65% smaller Area-Timing Products (ATP). Comparing mTC-PPA and 3DPmS-RRA, 3DPmS-RRA circuits are slightly faster than mTC-PPA on the average. In terms of ATP, mTC-PPA is superior by far and can be as small as 30% of 3DPmS-RRA. | en_US |
dc.identifier.doi | 10.1109/VLSI-SoC.2013.6673286 | |
dc.identifier.endpage | 265 | |
dc.identifier.isbn | 978-1-4799-0524-9 | |
dc.identifier.scopus | 2-s2.0-84899549514 | |
dc.identifier.startpage | 260 | |
dc.identifier.uri | http://hdl.handle.net/10679/664 | |
dc.identifier.uri | https://doi.org/10.1109/VLSI-SoC.2013.6673286 | |
dc.identifier.wos | 000332046100051 | |
dc.language.iso | eng | en_US |
dc.peerreviewed | yes | en_US |
dc.publicationstatus | published | en_US |
dc.publisher | IEEE | en_US |
dc.relation.ispartof | 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) | |
dc.relation.publicationcategory | International | |
dc.rights | restrictedAccess | |
dc.subject.keywords | Adders | en_US |
dc.subject.keywords | Logic circuits | en_US |
dc.title | Generating fast logic circuits for m-select n-port round Robin arbitration | en_US |
dc.type | conferenceObject | en_US |
dc.type.subtype | Conference paper | |
dspace.entity.type | Publication | |
relation.isOrgUnitOfPublication | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 | |
relation.isOrgUnitOfPublication.latestForDiscovery | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 |
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