A modeling study on the layout impact of with-in-die thickness range for STI CMP

Abstract

Chemical Mechanical Planarization process has a proven track record as an effective method for planarizing the wafer surface at multiple points of the semiconductor manufacturing flow. One of the most challenging aspects of the CMP process, particularly in applications like Shallow Trench Isolation (STI), is the difference in relative removal rates of the different materials that are being polished. A certain amount of over-polish is required to clear oxide on top of the nitride, however, this over-polish may also lead to significant problems like dishing and erosion (introducing additional topography after the film has been planarized). This work formulates a methodology to predict how this additional topography is modulated by incoming layout properties introducing a parameter to accurately characterize line and space width on a layout with random geometric shapes.