Browsing by Author "El-Sawy, Salma H."
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Master ThesisPublication Metadata only A 1GS/S, 9-BIT DAC I interleaved (2+1)-bit then 2-bit per cycle, reference free SAR ADC(2019-01-02) El-Sawy, Salma H.; Tekin, Ahmet; Tekin, Ahmet; Uğurdağ, Hasan Fatih; Karalar, T.; Department of Electrical and Electronics Engineering; El-Sawy, Salma H.This work presents a high speed, medium resolution Successive Approximation Register Analog to Digital Converter (SAR ADC) designed for low-noise, low- power satellite transceiver applications. The proposed system is a (2+1) then 2-bit per cycle SAR ADC of 1GS/s sampling rate, 9-bits resolution designed and characterized in a 65nm standard CMOS technology. The designed system resolves 9 bits with a special switching scheme in a total of 4 cycles per sample effectively. This is achieved by interleaving 4 Capacitive Digital to Analog Converter (C-DACs) of unit capacitance 1fF. Since the interleaving is limited to the passive DACs only which match well, the design does not suffer from the drawbacks of full interleaving. Hence, significantly better power efficiency and performance metrics have been obtained in comparison to regular interleaved ADCs. A special timing scheme with a single extra first-bit comparator is optimized to leave proper timing margins for every step from a single 4- GHz low noise clock source which is readily available in the 8- GHz direct conversion front-end. This comparator as well is reused as all the other active comparators in both interleaving phases. The proposed design achieves an effective number of bits (ENOB) of 8.5 bits at Nyquist with total power consumption of 15mW (1.25V supply), resulting in a Figure of Merit (FoM) of 38.37 fJ/conversion-step.