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Enabling difference-based dynamic partial self reconfiguration for large differences
(IEEE, 2013)
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ...
FPGA bitstream protection with PUFs, obfuscation, and multi-boot
(IEEE, 2011)
With the combination of PUFs, obfuscation, and multi-boot, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have ...
CPU design simplified
(IEEE, 2018-12-10)
The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ...
Defect-aware nanocrossbar logic mapping through matrix canonization using two-dimensional radix sort
(ACM, 2011-08)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ...
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
(IEEE, 2019)
As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the ...
Efficient combinational circuits for division by small integer constants
(IEEE, 2016)
Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of ...
A fast circuit topology for finding the maximum of n k-bit numbers
(IEEE, 2013)
Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) ...
Darbe i̇şaretleri̇ i̇çi̇n aşırı-hızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
(IEEE, 2012)
Bu çalışmada anlatılan donanım 1.5 GHz Analog-Sayısal- Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ...
Software UART: A use case for VSCPU worst-case execution time analyzer
(IEEE, 2019)
This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken ...
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