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Enabling difference-based dynamic partial self reconfiguration for large differences
(IEEE, 2013)
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ...
RoCoCo: row and column compression for high-performance multiplication on FPGAs
(IEEE, 2011)
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are ...
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