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RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
(IEEE, 2019)
As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the ...
Generating fast logic circuits for m-select n-port round Robin arbitration
(IEEE, 2013)
This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ...
Design and simulation of an optimal energy management strategy for plug-In electric vehicles
(IEEE, 2018)
Energy management algorithms play a critical role in improving the energy efficiency of modern electric vehicles. In order to be desirable for the customer, electric vehicles should be capable of long distance driving on ...
A multi-channel real time implementation of dual tree complex wavelet Transform in field programmable gate arrays
(Springer International Publishing, 2016)
In medical applications, biomedical acquisition systems (BASs) are frequently used in order to diagnose and monitor critical conditions such as stroke, epilepsy, Alzheimer disease, arrhythmias and etc. Biomedical signals ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
Fast one- and two-pick fixed-priority selection and muxing circuits
(IEEE, 2016)
Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with ...
Output domain downscaler
(ISCIS 2016: Computer and Information Sciences, 2016)
This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ...
Preface
(Springer Science+Business Media, 2015)
Efficient combinational circuits for division by small integer constants
(IEEE, 2016)
Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of ...
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