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Enabling difference-based dynamic partial self reconfiguration for large differences
(IEEE, 2013)
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ...
RoCoCo: row and column compression for high-performance multiplication on FPGAs
(IEEE, 2011)
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are ...
FPGA based particle identification in high energy physics experiments
(IEEE, 2012)
High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ...
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays
(IEEE, 2015)
Biomedical signals (BSs), which give information about the normal condition and also the inherent irregularities of our body, are expected to have non-stationary character due to the time-varying behavior of physiological ...
Darbe i̇şaretleri̇ i̇çi̇n aşırı-hızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
(IEEE, 2012)
Bu çalışmada anlatılan donanım 1.5 GHz Analog-Sayısal- Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ...
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