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25th IFIP/IEEE conference on very large scale integration (VLSI-SoC 2017)
(IEEE, 2018-02)
The 25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017) was held between 23 and 25 October in the landmark Yas Viceroy Hotel, overlooking the Formula 1 Yas Marina racetrack in Yas Island, Abu Dhabi, ...
FPGA based particle identification in high energy physics experiments
(IEEE, 2012)
High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ...
Combined AES + AEGIS architectures for high performance and lightweight security applications
(Springer International Publishing, 2014)
AES has been the prominent block cipher since its introduction as the standard. It has been the cipher used in almost all new applications that require solid, unbreakable security with reasonable resource usage. Several ...
CPU design simplified
(IEEE, 2018-12-10)
The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ...
Defect-aware nanocrossbar logic mapping through matrix canonization using two-dimensional radix sort
(ACM, 2011-08)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ...
Hardware division by small integer constants
(IEEE, 2017-12)
This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ...
Experiences on the road from EDA developer to designer to educator
(IEEE, 2013)
This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ...
Lossless look-up table compression for hardware implementation of transcendental functions
(IEEE, 2019)
Look-Up Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the ...
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration
(Elsevier, 2013-02)
This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. ...
RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
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