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Preface
(Springer Nature, 2019)
N/A
Fast two-pick n2n round-robin arbiter circuit
(IEEE, 2012-06)
A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked ...
Fast and efficient circuit topologies for finding the maximum of n k-bit numbers
(IEEE, 2014-08-01)
Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder ...
Fast parallel prefix logic circuits for n2n round-robin arbitration
(Elsevier, 2012-08)
An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains ...
Enabling difference-based dynamic partial self reconfiguration for large differences
(IEEE, 2013)
This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ...
FPGA bitstream protection with PUFs, obfuscation, and multi-boot
(IEEE, 2011)
With the combination of PUFs, obfuscation, and multi-boot, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have ...
Cost-benefit approach to degradation of electrolytic capacitors
(IEEE, 2014)
Aluminum electrolytic capacitors are widely used as a filter or bulky capacitor after rectification stages of switching power supplies (SMPS). Fly-back, forward, and resonant converter topologies, which are widely used in ...
Synthesis of clock trees for sampled-data analog IC blocks
(IEEE, 2013)
This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which ...
RoCoCo: row and column compression for high-performance multiplication on FPGAs
(IEEE, 2011)
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are ...
25th IFIP/IEEE conference on very large scale integration (VLSI-SoC 2017)
(IEEE, 2018-02)
The 25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017) was held between 23 and 25 October in the landmark Yas Viceroy Hotel, overlooking the Formula 1 Yas Marina racetrack in Yas Island, Abu Dhabi, ...
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