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Now showing items 11-20 of 36
Defect-aware nanocrossbar logic mapping through matrix canonization using two-dimensional radix sort
(ACM, 2011-08)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ...
Hardware division by small integer constants
(IEEE, 2017-12)
This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ...
Experiences on the road from EDA developer to designer to educator
(IEEE, 2013)
This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ...
Lossless look-up table compression for hardware implementation of transcendental functions
(IEEE, 2019)
Look-Up Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the ...
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration
(Elsevier, 2013-02)
This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. ...
RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
Generating fast logic circuits for m-select n-port round Robin arbitration
(IEEE, 2013)
This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ...
Design and simulation of an optimal energy management strategy for plug-In electric vehicles
(IEEE, 2018)
Energy management algorithms play a critical role in improving the energy efficiency of modern electric vehicles. In order to be desirable for the customer, electric vehicles should be capable of long distance driving on ...
A multi-channel real time implementation of dual tree complex wavelet Transform in field programmable gate arrays
(Springer International Publishing, 2016)
In medical applications, biomedical acquisition systems (BASs) are frequently used in order to diagnose and monitor critical conditions such as stroke, epilepsy, Alzheimer disease, arrhythmias and etc. Biomedical signals ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
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