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dc.contributor.authorKakacak, Ahmet
dc.contributor.authorGuzel, Aydın Emre
dc.contributor.authorCihangir, Ozan
dc.contributor.authorGören, S.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.date.accessioned2017-02-02T11:17:53Z
dc.date.available2017-02-02T11:17:53Z
dc.date.issued2017
dc.identifier.issn0167-9260
dc.identifier.urihttp://hdl.handle.net/10679/4764
dc.identifier.urihttp://www.sciencedirect.com/science/article/pii/S0167926016302115
dc.description.abstractWe present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) unique as it automatically generates placement pragmas, (iv) uses a ternary adder as a final adder to exploit FPGA's internal carry-chains, and (v) employs a novel GPC based row compression, which aims to reduce the width of the final adder. We wrote Verilog generators for our method as well as one leading work in the literature. For synthesis, we wrote a script that can do “binary search” for the optimum latency. Our extensive implementation results on Xilinx Virtex-6 FPGAs show that we almost always produce circuits with smaller latency (i.e., timing) and Area-Timing Product (ATP) compared to the state-of-the-art in the literature, by 18% and 12% (on the average), respectively. We also offer smaller latency compared to the HDL * operator by 9% on the average at a cost of 12% larger ATP on the average. We are worse in latency in 6 cases out of 33, in all of which synthesis maps * to DSP slices. We also include area and energy results on Virtex-6 as well as a limited amount of latency, area, and ATP results on Virtex-5 and Altera Stratix III.en_US
dc.language.isoengen_US
dc.publisherElsevieren_US
dc.relation.ispartofIntegration, the VLSI Journalen_US
dc.rightsrestrictedAccess
dc.titleFast multiplier generator for FPGAs with LUT based partial product generation and column/row compressionen_US
dc.typeArticleen_US
dc.peerreviewedyesen_US
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.volume57en_US
dc.identifier.startpage147en_US
dc.identifier.endpage157en_US
dc.identifier.wosWOS:000395609000015
dc.identifier.doi10.1016/j.vlsi.2016.12.012en_US
dc.subject.keywordsFast multipliersen_US
dc.subject.keywordsFPGAen_US
dc.subject.keywordsLook-up tableen_US
dc.subject.keywordsPartial product generationen_US
dc.subject.keywordsColumn compression treeen_US
dc.subject.keywordsCarry-save treeen_US
dc.subject.keywordsGeneralized parallel counteren_US
dc.identifier.scopusSCOPUS:2-s2.0-85008165502
dc.contributor.ozugradstudentKakacak, Ahmet
dc.contributor.ozugradstudentGuzel, Aydın Emre
dc.contributor.ozugradstudentCihangir, Ozan
dc.contributor.authorMale4


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