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dc.contributor.authorTosun, Mustafa
dc.date.accessioned2018-07-26T08:11:42Z
dc.date.available2018-07-26T08:11:42Z
dc.date.issued2017-01
dc.identifier.urihttp://hdl.handle.net/10679/5871
dc.identifier.urihttps://tez.yok.gov.tr
dc.identifier.urihttp://discover.ozyegin.edu.tr/iii/encore/record/C__Rb2122840?lang=eng
dc.descriptionThesis (M.A.)--Özyeğin University, Graduate School of Sciences and Engineering, Department of Electrical and Electronics Engineering, January 2017.
dc.description.abstractIn this thesis, we propose a class of logic architectures for multi-pick (m-pick) fixed-priority arbitration (FPA) and muxing. An m-pick FPA selects the m topmost requests out of n inputs with priority order. Arbiters usually drive multiplexers (muxes). Latency optimization of FPAs and mux trees have usually been handled separately in the literature. However, in some applications with circular data dependencies, it is the combined latency of the arbiter and muxing that needs to be optimized. Moreover, there is an ever growing need for throughput. This requires, for example, network switches that pick and mux m requests per cycle, where m > 1. This thesis starts with 1-pick priority based selection and muxing and then generalizes it to m-pick. A logic building block that we call \Saturated Adder" plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We have implemented the proposed architectures through Perl programs generating Verilog netlists and synthesized them using Synopsys Design Compiler with ARMArtisan TSMC 180 nm worst case standard-cell library. Through the results we have obtained, we demonstrated the trade-o ffs in the design of m-pick FPA and muxing.en_US
dc.description.abstractBu tezde, coklu(m)-se cim sabit- oncelikli i s d uzenleyici (FPA) ve coklay c (muxing) i cin bir mant k mimarisi s n f onermekteyiz. Bir coklu se cim FPA, n adet talep girdisinden en y uksek m tanesini oncelik s ras na g ore se cer. _ I s d uzenleyiciler genellikle coklay c lar (muxes) y onlendirir. FPA'ler ve coklay c a ga clar (mux trees) gecikme optimizasyonu cal smalar literat urde genellikle ayr olarak ele al nm st r. Bununla birlikte, dairesel veri ba g ml l klar olan baz uygulamalarda, optimize edilmesi gereken i s d uzenleyici ve coklay c n n gecikmesi bir araya getirilmi stir. Bunlar n d s nda, c kt i cin gittik ce artan bir ihtiya c vard r. Bu, orne gin m > 1 oldu gu zaman, her d ong ude m adet talebi se cen ve coklayan a g anahtarlar n gerektirir. Bu tez, sabit onceli ge dayanan tekli se cim ve coklama ile ba slar ve sonra coklu (m) se cim i cin genelle stirir. \S n rlanm s Toplay c " olarak adland rd g m z bir mant k olu sturma blo gu, 1-se cim ve 2-se cimli mimarileri basit problemler haline getirerek genellemede onemli bir rol oynamaktad r. onerilen mimarileri, verilog a g listeleri olu sturan Perl programlar vas tas yla uygulad k ve bunlar ARM-artisan TSMC 180 nm en k ot u durum standart h ucre k ut uphanesi ile Synopsys Design Compiler kullanarak sentezledik. Elde etti gimiz sonu clar vas tas yla, coklu (m) se cim FPA ve coklay c dizayn ndaki de gi stoku s dengesi tahlillerini g osterdik.
dc.language.isoengen_US
dc.rightsrestrictedAccess
dc.titleM-pick fixed-priority selection and muxingen_US
dc.title.alternativeM-seçmeli sabit-öncelikli seçme ve çoğullama
dc.typeMaster's thesisen_US
dc.contributor.advisorUğurdağ, Hasan Fatih
dc.contributor.committeeMemberUğurdağ, Hasan Fatih
dc.contributor.committeeMemberUğurdağ, S.G.
dc.contributor.committeeMemberAktemur, Tankut Barış
dc.publicationstatusUnpublisheden_US
dc.contributor.departmentÖzyeğin University
dc.subject.keywordsElectrical and Electronics Engineeringen_US
dc.contributor.ozugradstudentTosun, Mustafa
dc.contributor.authorMale1
dc.relation.publicationcategoryThesis - Institutional Graduate Student


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