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dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorBaskirt, O.
dc.date.accessioned2014-07-11T08:09:28Z
dc.date.available2014-07-11T08:09:28Z
dc.date.issued2012-08
dc.identifier.issn0026-2692
dc.identifier.urihttp://hdl.handle.net/10679/491
dc.identifier.urihttp://www.sciencedirect.com/science/article/pii/S0026269212000948
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.en_US
dc.description.abstractAn n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period.en_US
dc.language.isoengen_US
dc.publisherElsevieren_US
dc.relation.ispartofMicroelectronics Journal
dc.rightsrestrictedAccess
dc.titleFast parallel prefix logic circuits for n2n round-robin arbitrationen_US
dc.typeArticleen_US
dc.peerreviewedyesen_US
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.volume43
dc.identifier.issue8
dc.identifier.startpage573
dc.identifier.endpage581
dc.identifier.wosWOS:000306383500009
dc.identifier.doi10.1016/j.mejo.2012.04.005
dc.subject.keywordsCircuits for networkingen_US
dc.subject.keywordsComputer arithmeticen_US
dc.subject.keywordsLogic synthesisen_US
dc.subject.keywordsPriority encoderen_US
dc.subject.keywordsTiming optimizationen_US
dc.identifier.scopusSCOPUS:2-s2.0-84862533608
dc.contributor.authorMale1


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