Search
Now showing items 1-7 of 7
RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication
(IEEE, 2020-09)
A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to ...
Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01)
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques ...
Efficient FPGA implementation of field oriented control for 3-phase machine drives
(IEEE, 2020-09)
This paper presents an FPGA implementation of Field Oriented Control (FOC) method with high switching frequency for 3-phase machine drives. A common architecture has been constructed for both BrushLess DC motors (BLDC) and ...
Hardware implementation of field oriented control for three phase machine drives
(IEEE, 2020-10-05)
This paper presents a high switching frequency FPGA implementation of Maximum Torque Per Ampere (MTPA) and Flux Weakening which are branch of Field Oriented Control (FOC) method for 3-phase machine drives. A common ...
Rapid design of real-time image fusion on FPGA using HLS and other techniques
(IEEE, 2018)
During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which ...
Share this page