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Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
Output domain downscaler
(ISCIS 2016: Computer and Information Sciences, 2016)
This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ...
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