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Fast one- and two-pick fixed-priority selection and muxing circuits
(IEEE, 2016)
Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with ...
Using high-level synthesis for rapid design of video processing pipes
(IEEE, 2016)
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the ...
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
(Springer International Publishing, 2017)
FPGA acceleration of compute-intensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Data-parallel algorithms have an alternative platform for acceleration, ...
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