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Combined AES + AEGIS architectures for high performance and lightweight security applications
(Springer International Publishing, 2014)
AES has been the prominent block cipher since its introduction as the standard. It has been the cipher used in almost all new applications that require solid, unbreakable security with reasonable resource usage. Several ...
CPU design simplified
(IEEE, 2018-12-10)
The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ...
RImCom: raster-order image compressor for embedded video applications
(Springer International Publishing, 2017)
This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ...
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
(IEEE, 2019)
As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the ...
A multi-channel real time implementation of dual tree complex wavelet Transform in field programmable gate arrays
(Springer International Publishing, 2016)
In medical applications, biomedical acquisition systems (BASs) are frequently used in order to diagnose and monitor critical conditions such as stroke, epilepsy, Alzheimer disease, arrhythmias and etc. Biomedical signals ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
(Springer International Publishing, 2017)
FPGA acceleration of compute-intensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Data-parallel algorithms have an alternative platform for acceleration, ...
Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01)
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques ...
Software UART: A use case for VSCPU worst-case execution time analyzer
(IEEE, 2019)
This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken ...
Rapid design of real-time image fusion on FPGA using HLS and other techniques
(IEEE, 2018)
During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which ...
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