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CPU design simplified
(IEEE, 2018-12-10)
The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ...
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
(IEEE, 2019)
As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetric-key encryption algorithm for IoT devices. Compared to the ...
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
(Elsevier, 2017)
We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ...
Crucial topics in computer architecture education and a survey of textbooks and papers
(International Association of Engineers, 2020)
We have been teaching undergraduate computer architecture since 2012 in an unconventional way. Most undergraduate computer architecture courses are based on microprocessors, and they quickly move into advanced topics such ...
PYNQ-based rapid FPGA implementation of quantum key distribution
(IEEE, 2021)
In this paper, we present a real-time Quantum Key Distribution (QKD) implementation on Field Programmable Gate Arrays (FPGAs) for secure communication. We propose a novel methodology with a Python-based programming interface ...
Software UART: A use case for VSCPU worst-case execution time analyzer
(IEEE, 2019)
This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken ...
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