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Output domain downscaler
(ISCIS 2016: Computer and Information Sciences, 2016)
This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ...
Using high-level synthesis for rapid design of video processing pipes
(IEEE, 2016)
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the ...
Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01)
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques ...
Rapid design of real-time image fusion on FPGA using HLS and other techniques
(IEEE, 2018)
During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which ...
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