Show simple item record

dc.contributor.authorGören, S.
dc.contributor.authorOzkurt, O.
dc.contributor.authorYildiz, A.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorChakraborty, R. S.
dc.contributor.authorMukhopadhyay, D.
dc.date.accessioned2014-07-08T08:54:54Z
dc.date.available2014-07-08T08:54:54Z
dc.date.issued2013-02
dc.identifier.issn0045-7906
dc.identifier.urihttp://hdl.handle.net/10679/464
dc.identifier.urihttp://www.sciencedirect.com/science/article/pii/S0045790612001930#
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.en_US
dc.description.abstractThis paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. With the aid of this technique, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Through DPSR, our PUF implementation does not steal real estate from the encrypted design. We also present a new DPSR flow for Xilinx FPGAs, which is difference-based but still allows modular design. It works regardless of the amount of difference between Partial Reconfiguration (PR) modules and is called DPSR-LD, where LD stands for Large-Difference. DPSR-LD is an enabler especially for Spartan-6 FPGA family, as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. Our DPSR-LD also includes a controller that interfaces to the ICAP and can process compressed bitstreams. It is called ICAP+ and occupies only 1% of Spartan-6 slices.en_US
dc.language.isoengen_US
dc.publisherElsevieren_US
dc.relation.ispartofComputers & Electrical Engineering
dc.rightsrestrictedAccess
dc.titlePartial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfigurationen_US
dc.typeArticleen_US
dc.peerreviewedyesen_US
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID118293
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.volume39
dc.identifier.issue2
dc.identifier.startpage386
dc.identifier.endpage397
dc.identifier.wosWOS:000318454200021
dc.identifier.doi10.1016/j.compeleceng.2012.10.009
dc.subject.keywordsField-Programmable Gate Arraysen_US
dc.identifier.scopusSCOPUS:2-s2.0-84876282044
dc.contributor.authorMale1


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record


Share this page