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dc.contributor.authorGören, S.
dc.contributor.authorÖzkurt, Ö.
dc.contributor.authorTürk, Y.
dc.contributor.authorYıldız, A.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.date.accessioned2016-02-15T13:38:31Z
dc.date.available2016-02-15T13:38:31Z
dc.date.issued2013
dc.identifier.isbn978-1-4799-3525-3
dc.identifier.issn2162-0601
dc.identifier.urihttp://hdl.handle.net/10679/2346
dc.identifier.urihttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6727108
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.
dc.description.abstractThis paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.
dc.language.isoengen_US
dc.publisherIEEE
dc.relation.ispartof2013 8th IEEE Design and Test Symposium
dc.rightsrestrictedAccess
dc.titleEnabling difference-based dynamic partial self reconfiguration for large differencesen_US
dc.typeConference paperen_US
dc.peerreviewedyes
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID118293
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.startpage1
dc.identifier.endpage6
dc.identifier.wosWOS:000345773800035
dc.identifier.doi10.1109/IDT.2013.6727108
dc.subject.keywordsField programmable gate arrays
dc.subject.keywordsIntegrated circuit design
dc.subject.keywordsModules
dc.identifier.scopusSCOPUS:2-s2.0-84894457393
dc.contributor.authorMale1


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