Enabling difference-based dynamic partial self reconfiguration for large differences
dc.contributor.author | Gören, S. | |
dc.contributor.author | Özkurt, Ö. | |
dc.contributor.author | Türk, Y. | |
dc.contributor.author | Yıldız, A. | |
dc.contributor.author | Uğurdağ, Hasan Fatih | |
dc.date.accessioned | 2016-02-15T13:38:31Z | |
dc.date.available | 2016-02-15T13:38:31Z | |
dc.date.issued | 2013 | |
dc.identifier.isbn | 978-1-4799-3525-3 | |
dc.identifier.issn | 2162-0601 | |
dc.identifier.uri | http://hdl.handle.net/10679/2346 | |
dc.identifier.uri | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6727108 | |
dc.description | Due to copyright restrictions, the access to the full text of this article is only available via subscription. | |
dc.description.abstract | This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression. | |
dc.language.iso | eng | en_US |
dc.publisher | IEEE | |
dc.relation.ispartof | 2013 8th IEEE Design and Test Symposium | |
dc.rights | restrictedAccess | |
dc.title | Enabling difference-based dynamic partial self reconfiguration for large differences | en_US |
dc.type | Conference paper | en_US |
dc.peerreviewed | yes | |
dc.publicationstatus | published | en_US |
dc.contributor.department | Özyeğin University | |
dc.contributor.authorID | (ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih | |
dc.contributor.ozuauthor | Uğurdağ, Hasan Fatih | |
dc.identifier.startpage | 1 | |
dc.identifier.endpage | 6 | |
dc.identifier.wos | WOS:000345773800035 | |
dc.identifier.doi | 10.1109/IDT.2013.6727108 | |
dc.subject.keywords | Field programmable gate arrays | |
dc.subject.keywords | Integrated circuit design | |
dc.subject.keywords | Modules | |
dc.identifier.scopus | SCOPUS:2-s2.0-84894457393 | |
dc.contributor.authorMale | 1 | |
dc.relation.publicationcategory | Conference Paper - International - Institutional Academic Staff |
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