Search
Now showing items 31-40 of 60
Software defined VLC system: implementation and performance evaluation
(IEEE, 2015)
This paper presents the implementation of an IEEE standard-based Visible Light Communication (VLC) system using software defined radio (SDR) approach. Based on widely used SDR platform Universal Software Radio Peripheral ...
Using high-level synthesis for rapid design of video processing pipes
(IEEE, 2016)
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the ...
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays
(IEEE, 2015)
Biomedical signals (BSs), which give information about the normal condition and also the inherent irregularities of our body, are expected to have non-stationary character due to the time-varying behavior of physiological ...
Referanssız görüntü bloklanma ölçümü için yeni bir yöntem
(IEEE, 2014)
Internet’te ve servis sağlayıcı ağlarında video trafiğinin tavan yaptığı günümüzde otomatik görüntü kalitesi ölçümünün faydaları aşikardır. Bu ölçümlerin birçok uygulamada gerçekzamanlı yapılması gerekir ve de bu “Referanssız” ...
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
(Springer International Publishing, 2017)
FPGA acceleration of compute-intensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Data-parallel algorithms have an alternative platform for acceleration, ...
Welcome from the general chairs
(IEEE, 2013)
FPGA implementation of a low latency and high SFDR direct digital synthesizer for resource-efficient quantum-enhanced communication
(IEEE, 2020-09)
A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to ...
A fast circuit topology for finding the maximum of n k-bit numbers
(IEEE, 2013)
Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) ...
Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01)
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques ...
Darbe i̇şaretleri̇ i̇çi̇n aşırı-hızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
(IEEE, 2012)
Bu çalışmada anlatılan donanım 1.5 GHz Analog-Sayısal- Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ...
Share this page