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(Springer Nature, 2019)
Fast two-pick n2n round-robin arbiter circuit
A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked ...
Fast and efficient circuit topologies for finding the maximum of n k-bit numbers
Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder ...
Fast parallel prefix logic circuits for n2n round-robin arbitration
An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains ...
RoCoCo: row and column compression for high-performance multiplication on FPGAs
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are ...
25th IFIP/IEEE conference on very large scale integration (VLSI-SoC 2017)
The 25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017) was held between 23 and 25 October in the landmark Yas Viceroy Hotel, overlooking the Formula 1 Yas Marina racetrack in Yas Island, Abu Dhabi, ...
FPGA based particle identification in high energy physics experiments
High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ...
Hardware division by small integer constants
This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ...
Experiences on the road from EDA developer to designer to educator
This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ...
Lossless look-up table compression for hardware implementation of transcendental functions
Look-Up Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the ...
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