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dc.contributor.authorTemizkan, Fatih
dc.descriptionThesis (M.A.)--Özyeğin University, Graduate School of Sciences and Engineering, Department of Electrical and Electronics Engineering, August 2012.en_US
dc.description.abstractIn this thesis, we propose two multi(m)-pick Round Robin Arbiter (RRA) architectures. An m-pick RRA selects the m topmost requests out of n inputs with priority order indicated by an internally kept pointer (with an update policy that ensures fairness among requestors). The architectures that we propose are m-pick Thermo Coded-Parallel Prefix Arbiter (TC-PPA) and Three-Dimensional Programmable m-Selector RRA (3DPmS-RRA). Prior to this thesis, these two architectures existed in the literature as 2-pick and 1-pick arbiters, respectively. Our main contribution to the literature is the generalization of these architectures to m-pick. A logic building block that we call ?Saturated Adder? plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We developed six different variants of 3DPmS-RRA and eight different variants of m-pick TC-PPA. We wrote automated HDL code generators for all variants as well as Cascade Architecture, which is a straight-forward way of implementing a multi-pick RRA using 1-pick Programmable Priority Encoders. Then, all multi-pick architectures were verified and synthesized. Our experimental results show that 3DPmS-RRA architecture is the best choice for all pick sizes (except 2-pick) when timing is the primary design criterion. However, when area is more critical, TC-PPA architecture performs better. It is worthwhile to note that in terms of timing 3DPmS-RRA is better than TC-PPA by a mere 8% at the most based on our synthesis results. However, when we consider area, TC-PPA has significant improvements over 3DPmS-RRA, up to 53%.en_US
dc.titleMulti-pick round robin arbiteren_US
dc.typeMaster's thesisen_US
dc.contributor.advisorUğurdağ, H. Fatih
dc.contributor.committeeMemberUğurdağ, H. Fatih
dc.contributor.committeeMemberErdem, Tanju
dc.contributor.committeeMemberAktemur, Tankut Barış
dc.contributor.departmentÖzyeğin University
dc.subject.keywordsComputer arithmeticen_US
dc.subject.keywordsDigital circuitsen_US
dc.subject.keywordsDigital designen_US
dc.subject.keywordsLogic synthesisen_US
dc.subject.keywordsTiming optimizationen_US
dc.subject.keywordsAutomatic HDL code generationen_US
dc.subject.keywordsDesign automationen_US
dc.contributor.ozugradstudentTemizkan, Fatih
dc.relation.publicationcategoryThesis - Institutional Graduate Student

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