Browsing by Author "Gören, S."
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CPU design simplified
Yıldız, A.; Uğurdağ, Hasan Fatih; Aktemur, Tankut Barış; İskender, Deniz; Gören, S. (IEEE, 20181210)The first goal of this paper is to introduce a simple and customizable soft CPU named VerySimpleCPU (VSCPU), which could be easily implemented on FPGAs with a complete toolchain including instruction set simulator, assembler, ... 
Darbe i̇şaretleri̇ i̇çi̇n aşırıhızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
Başaran, A.; Uğurdağ, Hasan Fatih; Akdoğan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)Bu çalışmada anlatılan donanım 1.5 GHz AnalogSayısal Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ... 
Defectaware nanocrossbar logic mapping through matrix canonization using twodimensional radix sort
Gören, S.; Uğurdağ, Hasan Fatih; Palaz, O. (ACM, 201108)Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuckopen/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ... 
Efficient combinational circuits for division by small integer constants
Uğurdağ, Hasan Fatih; Bayram, A.; Levent, Vecdi Levent; Gören, S. (IEEE, 2016)Division of an integer by an integer constant is a widely used operation and hence justifies a customized efficient implementation. There are various versions of this operation. This paper attacks a particular version of ... 
Enabling differencebased dynamic partial self reconfiguration for large differences
Gören, S.; Özkurt, Ö.; Türk, Y.; Yıldız, A.; Uğurdağ, Hasan Fatih (IEEE, 2013)This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ... 
Fast and efficient circuit topologies for finding the maximum of n kbit numbers
Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G. (IEEE, 20140801)Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with kbits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximumfinder ... 
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
Varıcı, Abdullah; Sağlam, Gürol; İpek, Seçkin; Yıldız, A.; Gören, S.; Aysu, A.; İskender, Deniz; Aktemur, Tankut Barış; Uğurdağ, Hasan Fatih (IEEE, 2019)As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetrickey encryption algorithm for IoT devices. Compared to the ... 
A fast circuit topology for finding the maximum of n kbit numbers
Yuce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dundar, G. (IEEE, 2013)Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (lowlatency) ... 
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Kakacak, Ahmet; Guzel, Aydın Emre; Cihangir, Ozan; Gören, S.; Uğurdağ, Hasan Fatih (Elsevier, 2017)We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ... 
FPGA based particle identification in high energy physics experiments
Uğurdağ, Hasan Fatih; Başaran, A.; Akdogan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)High energy physics experiments require onthefly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ... 
FPGA bitstream protection with PUFs, obfuscation, and multiboot
Gören, S.; Özkurt, Ö.; Yıldız, Abdullah; Uğurdağ, Hasan Fatih (IEEE, 2011)With the combination of PUFs, obfuscation, and multiboot, we are able to do the equivalent of partial bitstream encryption on lowcost FPGAs, which is only featured on highend FPGAs. Lowcost FPGAs do not even have ... 
Generating fast logic circuits for mselect nport round Robin arbitration
Uğurdağ, Hasan Fatih; Temizkan, F.; Gören, S. (IEEE, 2013)This paper generalizes the problem of Round Robin Arbitration (RRA) from 1select to mselect (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ... 
Lossless lookup table compression for hardware implementation of transcendental functions
Gener, Y. S.; Gören, S.; Uğurdağ, Hasan Fatih (IEEE, 2019)LookUp Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the ... 
Output domain downscaler
Büyükmıhçı, M.; Levent, Vecdi Emre; Guzel, Aydın Emre; Ates, Ozgur; Tosun, Mustafa; Akgün, T.; Erbas, C.; Gören, S.; Uğurdağ, Hasan Fatih (ISCIS 2016: Computer and Information Sciences, 2016)This paper offers an areaefficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ... 
Partial bitstream protection for lowcost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration
Gören, S.; Ozkurt, O.; Yildiz, A.; Uğurdağ, Hasan Fatih; Chakraborty, R. S.; Mukhopadhyay, D. (Elsevier, 201302)This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. ... 
Software UART: A use case for VSCPU worstcase execution time analyzer
Yıldız, A.; İskender, Deniz; Özlü, G.; Uğurdağ, Hasan Fatih; Aktemur, Tankut Barış; Gören, S. (IEEE, 2019)This paper presents our early results of the development of a WorstCase Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken ...
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