Browsing by Author "Dündar, G."
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Analog clock tree synthesis
Güner, Gökhan (2014-01)Anahtarlamalı analog devrelerin (AAD) saat ağı tasarımı ciddi zaman gerektiren ve yongaların tekrar elden geçirilmesine sebep olabilecek hatalara açık, elle yapılan bir işlemdir. Bu probleme otomatik ya da yarı-otomatik ... -
Distance and power based experimental verification of channel model in visible light communication
Kısacık, Rıfat; Efe, B. C.; Pusane, A. E.; Uysal, Murat; Baykas, T.; Dündar, G.; Yalcinkaya, A. D. (IEEE, 2019)In this work, a channel model for line-of-sight (LOS) in visible light communication is elaborated. In the proposed channel model, there is no optical component, such as filter or lens, between the transmitting LED and the ... -
Fast and efficient circuit topologies for finding the maximum of n k-bit numbers
Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G. (IEEE, 2014-08-01)Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder ... -
Opto-electronic receiver system with post-equalization for visible light communications
Kısacık, Rıfat; Erkınacı, T.; Yağan, M. Y.; Pusane, A. E.; Uysal, Murat; Baykaş, T.; Dündar, G.; Yalçınkaya, A. D. (IEEE, 2020-10-05)In this work, A significant increase in the data rate is achieved by designing an opto-electronic receiver for the visible light communication system. LEDs used at the transmitter side in the visible light communication ... -
Synthesis of clock trees for sampled-data analog IC blocks
Yüce, B.; Korkmaz, S.; Esen, V. B.; Temizkan, Fatih; Tunç, Cihan; Güner, Gökhan; Başkaya, I. F.; Agi, İ.; Dündar, G.; Uğurdağ, Hasan Fatih (IEEE, 2013)This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which ...
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