Yüce, B.Korkmaz, S.Esen, V. B.Temizkan, FatihTunç, CihanGüner, GökhanBaşkaya, I. F.Agi, İ.Dündar, G.Uğurdağ, Hasan Fatih2016-02-152016-02-152013978-1-4799-2095-2http://hdl.handle.net/10679/2352https://doi.org/10.1109/EWDTS.2013.6673154Due to copyright restrictions, the access to the full text of this article is only available via subscription.This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.enginfo:eu-repo/semantics/restrictedAccessConference paper1400033204240007610.1109/EWDTS.2013.6673154Analogue integrated circuitsAnalogue-digital conversionElectronic engineering computingIntegrated circuit designIntegrated circuit testing2-s2.0-84893450993