Levent, Vecdi EmreGüzel, Aydın EmreTosun, M.Büyükmıhcı, MertAydın, FurkanGoren, S.Erbas, C.Akgun, T.Uğurdağ, Hasan Fatih2020-09-022020-09-022019-011939-8018http://hdl.handle.net/10679/6875https://doi.org/10.1007/s11265-018-1402-7This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off.engrestrictedAccessarticle9119311300045533550000810.1007/s11265-018-1402-7Hardware IP generationReal-time video processingHigh-level synthesisFPGAOptical flowNested pipelining2-s2.0-85053609958