Gören, S.Özkurt, Ö.Türk, Y.Yıldız, A.Uğurdağ, Hasan Fatih2016-02-152016-02-152013978-1-4799-3525-32162-0601http://hdl.handle.net/10679/2346https://doi.org/10.1109/IDT.2013.6727108Due to copyright restrictions, the access to the full text of this article is only available via subscription.This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.engrestrictedAccessconferenceObject1600034577380003510.1109/IDT.2013.6727108Field programmable gate arraysIntegrated circuit designModules2-s2.0-84894457393