Temizkan, Fatih2014-06-272014-06-272012-08http://hdl.handle.net/10679/388http://discover.ozyegin.edu.tr/iii/encore/record/C__Rb1249617?lang=enghttps://tez.yok.gov.tr/In this thesis, we propose two multi(m)-pick Round Robin Arbiter (RRA) architectures. An m-pick RRA selects the m topmost requests out of n inputs with priority order indicated by an internally kept pointer (with an update policy that ensures fairness among requestors). The architectures that we propose are m-pick Thermo Coded-Parallel Prefix Arbiter (TC-PPA) and Three-Dimensional Programmable m-Selector RRA (3DPmS-RRA). Prior to this thesis, these two architectures existed in the literature as 2-pick and 1-pick arbiters, respectively. Our main contribution to the literature is the generalization of these architectures to m-pick. A logic building block that we call ?Saturated Adder? plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We developed six different variants of 3DPmS-RRA and eight different variants of m-pick TC-PPA. We wrote automated HDL code generators for all variants as well as Cascade Architecture, which is a straight-forward way of implementing a multi-pick RRA using 1-pick Programmable Priority Encoders. Then, all multi-pick architectures were verified and synthesized. Our experimental results show that 3DPmS-RRA architecture is the best choice for all pick sizes (except 2-pick) when timing is the primary design criterion. However, when area is more critical, TC-PPA architecture performs better. It is worthwhile to note that in terms of timing 3DPmS-RRA is better than TC-PPA by a mere 8% at the most based on our synthesis results. However, when we consider area, TC-PPA has significant improvements over 3DPmS-RRA, up to 53%.enginfo:eu-repo/semantics/restrictedAccessMaster's thesisUğurdağ, H. FatihComputer arithmeticDigital circuitsDigital designLogic synthesisTiming optimizationAutomatic HDL code generationDesign automationASIC1249617