Büyükmıhçı, M.Levent, Vecdi EmreGuzel, Aydın EmreAtes, OzgurTosun, MustafaAkgün, T.Erbas, C.Gören, S.Uğurdağ, Hasan Fatih2017-01-262017-01-2620161865-0929http://hdl.handle.net/10679/4734https://doi.org/10.1007/978-3-319-47217-1_28This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with Edge Detection and Sharpening Spatial Filter. We compare ODD to a straight-forward implementation of the same combination of methods, which we call Input Domain Downscaler (IDD). IDD tries to output a new pixel of the downscaled video frame every time a new pixel of the original video frame is received. However, every once in a while, there is no downscaled pixel to produce, and hence, IDD stalls. IDD sometimes also skips a complete row of input pixels. ODD, on the other hand, spreads out the job of producing downscaled pixels almost uniformly over a frame. As a result, ODD is able to employ more resource sharing, i.e., can do the same job with fewer arithmetic units, thus offers a more area-efficient solution than IDD. In this paper, we explain how ODD and IDD work and also share their FPGA synthesis results.engrestrictedAccessconferenceObject65926226900038951460002810.1007/978-3-319-47217-1_28Image interpolation2-s2.0-84989306816