Uğurdağ, Hasan FatihTemizkan, FatihBaskirt, O.Yuce, B.2014-07-112014-07-112012-060013-5194http://hdl.handle.net/10679/493https://doi.org/10.1049/el.2012.0307Due to copyright restrictions, the access to the full text of this article is only available via subscription.A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked requests with (at most) two-hot n-bit output. A round-robin arbiter is fair to its requesters and does this by repeatedly moving its highest priority pointer to the position immediately next to the second requester picked. Presented is the circuit architecture and VLSI implementation of a new scalable two-pick round-robin arbiter with low latency, which is compared with previous work based on logic synthesis results.enginfo:eu-repo/semantics/restrictedAccessArticle481375976000030670770001310.1049/el.2012.0307Asynchronous circuitsLogic design2-s2.0-84864215220