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dc.contributor.authorGener, Y. S.
dc.contributor.authorAydın, F.
dc.contributor.authorGören, S.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.editorMetzler, C.
dc.contributor.editorGaillardon, P.-E.
dc.contributor.editorMicheli, G. de
dc.contributor.editorSilva-Cardenas, C.
dc.contributor.editorReis, R.
dc.date.accessioned2021-10-11T13:25:03Z
dc.date.available2021-10-11T13:25:03Z
dc.date.issued2020
dc.identifier.isbn978-303053272-7
dc.identifier.issn1868-4238en_US
dc.identifier.urihttp://hdl.handle.net/10679/7632
dc.identifier.urihttps://link.springer.com/chapter/10.1007/978-3-030-53273-4_13
dc.description.abstractLook-Up Table (LUT) implementation of complicated functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. If the function is smooth, MultiPartite table method (MP) can circumvent the area problem by breaking up the implementation into multiple smaller LUTs. However, even some of these smaller LUTs may be big in high accuracy MP implementations. Lossless LUT compression can be applied to these LUTs to further improve area and even timing in some cases. The state-of-the-art in the literature decomposes the Table of Initial Values (TIV) of MP into a table of pivots and tables of differences from the pivots. Our technique instead places differences of consecutive elements in the difference tables and result in a smaller range of differences that fit in fewer bits. Constraining the difference of consecutive input values, hence semi-random access, allows us to further optimize designs. We also propose variants of our techniques with variable length coding. We implemented Verilog generators of MP for sine and exponential using conventional LUT as well as different versions of the state-of-the-art and our technique. We synthesized the generated designs on FPGA and found that our techniques produce up to 29% improvement in area, 11% improvement in timing, and 26% improvement in area-time product over the state-of-the-art.en_US
dc.language.isoengen_US
dc.publisherSpringeren_US
dc.relation.ispartofVLSI-SoC: New Technology Enabler, Part of the IFIP Advances in Information and Communication Technology book series
dc.rightsrestrictedAccess
dc.titleSemi- and fully-random access LUTs for smooth functionsen_US
dc.typeConference paperen_US
dc.publicationstatusPublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.volume586en_US
dc.identifier.startpage279en_US
dc.identifier.endpage306en_US
dc.identifier.doi10.1007/978-3-030-53273-4_13en_US
dc.identifier.scopusSCOPUS:2-s2.0-85089234401
dc.contributor.authorMale1
dc.relation.publicationcategoryConference Paper - International - Institution Academic Staff


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