Publication: Combined AES + AEGIS architectures for high performance and lightweight security applications
dc.contributor.author | Şahin, Furkan | |
dc.contributor.author | Uğurdağ, Hasan Fatih | |
dc.contributor.author | Yalçın, T. | |
dc.contributor.department | Electrical & Electronics Engineering | |
dc.contributor.ozuauthor | UĞURDAĞ, Hasan Fatih | |
dc.contributor.ozugradstudent | Şahin, Furkan | |
dc.date.accessioned | 2016-02-15T13:38:32Z | |
dc.date.available | 2016-02-15T13:38:32Z | |
dc.date.issued | 2014 | |
dc.description.abstract | AES has been the prominent block cipher since its introduction as the standard. It has been the cipher used in almost all new applications that require solid, unbreakable security with reasonable resource usage. Several versions of AES have been implemented in both hardware and software platforms with all kinds of design targets varying from high-performance to lightweight. With the widespread Internet, authenticated encryption (AE) has gained an unprecedented popularity, making AES the logical choice for AE implementations. While there already exists standardized modes that allow AES to be used for AE, more recently, special AE schemes that utilize AES in its native form (or with minimal modifications) have emerged. While these modes claim better performance and resource usage, very few implementations exist to support these claims, yet. In our work, we combine AES with one of the most recent AE ciphers, namely AEGIS, in an effort to analyse the combined performance of the two ciphers. | |
dc.identifier.doi | 10.1007/978-3-319-09879-1_22 | |
dc.identifier.endpage | 224 | |
dc.identifier.isbn | 978-3-319-09879-1 | |
dc.identifier.scopus | 2-s2.0-84906308914 | |
dc.identifier.startpage | 213 | |
dc.identifier.uri | http://hdl.handle.net/10679/2354 | |
dc.identifier.uri | https://doi.org/10.1007/978-3-319-09879-1_22 | |
dc.language.iso | eng | en_US |
dc.peerreviewed | yes | |
dc.publicationstatus | published | en_US |
dc.publisher | Springer International Publishing | |
dc.relation.ispartof | ICT Innovations 2014 (Advances in Intelligent Systems and Computing) | |
dc.relation.publicationcategory | International | |
dc.rights | restrictedAccess | |
dc.subject.keywords | Encryption | |
dc.subject.keywords | Authenticated encryption | |
dc.subject.keywords | AES | |
dc.subject.keywords | AEGIS | |
dc.subject.keywords | High performance | |
dc.subject.keywords | Lightweight | |
dc.subject.keywords | Security | |
dc.subject.keywords | FPGA | |
dc.subject.keywords | ASIC | |
dc.title | Combined AES + AEGIS architectures for high performance and lightweight security applications | en_US |
dc.type | bookPart | en_US |
dspace.entity.type | Publication | |
relation.isOrgUnitOfPublication | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 | |
relation.isOrgUnitOfPublication.latestForDiscovery | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 |