Publication:
Software UART: A use case for VSCPU worst-case execution time analyzer

dc.contributor.authorYıldız, A.
dc.contributor.authorİskender, Deniz
dc.contributor.authorÖzlü, G.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorAktemur, Tankut Barış
dc.contributor.authorGören, S.
dc.contributor.departmentElectrical & Electronics Engineering
dc.contributor.departmentComputer Science
dc.contributor.ozuauthorUĞURDAĞ, Hasan Fatih
dc.contributor.ozuauthorAKTEMUR, Tankut Bariş
dc.contributor.ozugradstudentİskender, Deniz
dc.date.accessioned2020-09-14T11:05:21Z
dc.date.available2020-09-14T11:05:21Z
dc.date.issued2019
dc.description.abstractThis paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken by each function as output. A software UART system eliminates the need to employ a dedicated hardware for RS232 interface and makes directly use of the processor instead. For this purpose, we designed and implemented a memory-mapped system which has access to UART pins and is capable of setting and sampling these pins from software by a method of bit banging. We used the output of our WCET analyzer to approximate the actual bit times for a specific UART baud rate. By successfully testing and verifying our software UART, we showed that our WCET analyzer could be used to estimate runtime of tasks in an application. Although development of the WCET analyzer is ongoing, the results are promising.en_US
dc.description.sponsorshipTÜBİTAK
dc.identifier.doi10.1109/UBMK.2019.8907220en_US
dc.identifier.isbn978-172813964-7
dc.identifier.scopus2-s2.0-85076209436
dc.identifier.urihttp://hdl.handle.net/10679/6947
dc.identifier.urihttps://doi.org/10.1109/UBMK.2019.8907220
dc.identifier.wos000609879900096
dc.language.isoengen_US
dc.publicationstatusPublisheden_US
dc.publisherIEEEen_US
dc.relationinfo:eu-repo/grantAgreement/TUBITAK/1001 - Araştırma/117E090
dc.relation.ispartof2019 4th International Conference on Computer Science and Engineering (UBMK)
dc.relation.publicationcategoryInternational
dc.rightsrestrictedAccess
dc.subject.keywordsWCETen_US
dc.subject.keywordsUARTen_US
dc.subject.keywordsCPUen_US
dc.subject.keywordsBit bangingen_US
dc.subject.keywordsFPGAen_US
dc.subject.keywordsProces-soren_US
dc.titleSoftware UART: A use case for VSCPU worst-case execution time analyzeren_US
dc.typeconferenceObjecten_US
dspace.entity.typePublication
relation.isOrgUnitOfPublication7b58c5c4-dccc-40a3-aaf2-9b209113b763
relation.isOrgUnitOfPublication85662e71-2a61-492a-b407-df4d38ab90d7
relation.isOrgUnitOfPublication.latestForDiscovery7b58c5c4-dccc-40a3-aaf2-9b209113b763

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