Publication: Software UART: A use case for VSCPU worst-case execution time analyzer
dc.contributor.author | Yıldız, A. | |
dc.contributor.author | İskender, Deniz | |
dc.contributor.author | Özlü, G. | |
dc.contributor.author | Uğurdağ, Hasan Fatih | |
dc.contributor.author | Aktemur, Tankut Barış | |
dc.contributor.author | Gören, S. | |
dc.contributor.department | Electrical & Electronics Engineering | |
dc.contributor.department | Computer Science | |
dc.contributor.ozuauthor | UĞURDAĞ, Hasan Fatih | |
dc.contributor.ozuauthor | AKTEMUR, Tankut Bariş | |
dc.contributor.ozugradstudent | İskender, Deniz | |
dc.date.accessioned | 2020-09-14T11:05:21Z | |
dc.date.available | 2020-09-14T11:05:21Z | |
dc.date.issued | 2019 | |
dc.description.abstract | This paper presents our early results of the development of a Worst-Case Execution Time (WCET) analyzer for VSCPU by implementing a software UART system. Our WCET analyzer takes a C program as input and gives the time taken by each function as output. A software UART system eliminates the need to employ a dedicated hardware for RS232 interface and makes directly use of the processor instead. For this purpose, we designed and implemented a memory-mapped system which has access to UART pins and is capable of setting and sampling these pins from software by a method of bit banging. We used the output of our WCET analyzer to approximate the actual bit times for a specific UART baud rate. By successfully testing and verifying our software UART, we showed that our WCET analyzer could be used to estimate runtime of tasks in an application. Although development of the WCET analyzer is ongoing, the results are promising. | en_US |
dc.description.sponsorship | TÜBİTAK | |
dc.identifier.doi | 10.1109/UBMK.2019.8907220 | en_US |
dc.identifier.isbn | 978-172813964-7 | |
dc.identifier.scopus | 2-s2.0-85076209436 | |
dc.identifier.uri | http://hdl.handle.net/10679/6947 | |
dc.identifier.uri | https://doi.org/10.1109/UBMK.2019.8907220 | |
dc.identifier.wos | 000609879900096 | |
dc.language.iso | eng | en_US |
dc.publicationstatus | Published | en_US |
dc.publisher | IEEE | en_US |
dc.relation | info:eu-repo/grantAgreement/TUBITAK/1001 - Araştırma/117E090 | |
dc.relation.ispartof | 2019 4th International Conference on Computer Science and Engineering (UBMK) | |
dc.relation.publicationcategory | International | |
dc.rights | restrictedAccess | |
dc.subject.keywords | WCET | en_US |
dc.subject.keywords | UART | en_US |
dc.subject.keywords | CPU | en_US |
dc.subject.keywords | Bit banging | en_US |
dc.subject.keywords | FPGA | en_US |
dc.subject.keywords | Proces-sor | en_US |
dc.title | Software UART: A use case for VSCPU worst-case execution time analyzer | en_US |
dc.type | conferenceObject | en_US |
dspace.entity.type | Publication | |
relation.isOrgUnitOfPublication | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 | |
relation.isOrgUnitOfPublication | 85662e71-2a61-492a-b407-df4d38ab90d7 | |
relation.isOrgUnitOfPublication.latestForDiscovery | 7b58c5c4-dccc-40a3-aaf2-9b209113b763 |
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