Browsing by Author "Uğurdağ, Hasan Fatih"
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Enabling differencebased dynamic partial self reconfiguration for large differences
Gören, S.; Özkurt, Ö.; Türk, Y.; Yıldız, A.; Uğurdağ, Hasan Fatih (IEEE, 2013)This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ... 
Energy consumption modeling and optimization of speed profile for plugin electric vechiles
Tasooji, Tohid Kargar (201805)In recent years, there is a surge in research on Plugin Electric Vehicles (PEVs), as PEVs are one of the ways that we can reduce carbon emissions. Dramatic cost reduction in PEVs has resulted in their becoming mainstream ... 
Experiences on the road from EDA developer to designer to educator
Uğurdağ, Hasan Fatih (IEEE, 2013)This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ... 
Fast and efficient circuit topologies for finding the maximum of n kbit numbers
Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G. (IEEE, 20140801)Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with kbits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximumfinder ... 
Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension
Varıcı, Abdullah; Sağlam, Gürol; İpek, Seçkin; Yıldız, A.; Gören, S.; Aysu, A.; İskender, Deniz; Aktemur, Tankut Barış; Uğurdağ, Hasan Fatih (IEEE, 2019)As Internet of Things (IoT) technology becomes widespread, the importance of information security increases. PRESENT algorithm is a major lightweight symmetrickey encryption algorithm for IoT devices. Compared to the ... 
A fast circuit topology for finding the maximum of n kbit numbers
Yuce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dundar, G. (IEEE, 2013)Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (lowlatency) ... 
Fast incremental least square pose estimation for hardware implementation with rolling shutter camera
Güzel, Aydın Emre; Hisar, Dilara; Claesen, L.; Uğurdağ, Hasan Fatih (IEEE, 20201005)6 DoF position and orientation estimation is vital for many realtime applications. It is essential to meet low latency, high accuracy and reliability requirements, especially when used for realtime haptic feedback ... 
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Kakacak, Ahmet; Guzel, Aydın Emre; Cihangir, Ozan; Gören, S.; Uğurdağ, Hasan Fatih (Elsevier, 2017)We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ... 
Fast one and twopick fixedpriority selection and muxing circuits
Tosun, Mustafa; Özkan, M. Akif; Güzel, Aydin Emre; Uğurdağ, Hasan Fatih (IEEE, 2016)Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with ... 
Fast parallel prefix logic circuits for n2n roundrobin arbitration
Uğurdağ, Hasan Fatih; Baskirt, O. (Elsevier, 201208)An n2n roundrobin arbiter (RRA) searches its n inputs for a 1, starting from the highestpriority input. It picks the first 1 and outputs its index in onehot encoding. RRA aims to be fair to its inputs and maintains ... 
Fast twopick n2n roundrobin arbiter circuit
Uğurdağ, Hasan Fatih; Temizkan, Fatih; Baskirt, O.; Yuce, B. (IEEE, 201206)A regular (onepick) roundrobin arbiter circuit picks one active requester (if any) out of n requesters. A twopick roundrobin arbiter selects up to two requesters. An n2n twopick roundrobin arbiter indicates the picked ... 
FPGA based DCOOFDM PHY transceiver for VLC systems
Levent, V. E.; Sağlam, Gürol; Uğurdağ, Hasan Fatih; Annafianto, Nur Fajar Rizqi; Aydın, Furkan; Tesfay, Shewit Weldu; Mohamed, Bassam Aly Abdelrahman; Elamassie, Mohammed; Kebapçı, Burak; Uysal, Murat (IEEE, 2019)Satisfying the demand for high bandwidth and low latency in Visible Light Communication (VLC) systems is a difficult challenge. VLC channels exhibit frequencyselectiveness at peakspeeds. This phenomenon generates a serious ... 
FPGA based particle identification in high energy physics experiments
Uğurdağ, Hasan Fatih; Başaran, A.; Akdogan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)High energy physics experiments require onthefly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ... 
FPGA bitstream protection with PUFs, obfuscation, and multiboot
Gören, S.; Özkurt, Ö.; Yıldız, Abdullah; Uğurdağ, Hasan Fatih (IEEE, 2011)With the combination of PUFs, obfuscation, and multiboot, we are able to do the equivalent of partial bitstream encryption on lowcost FPGAs, which is only featured on highend FPGAs. Lowcost FPGAs do not even have ... 
FPGA implementation of a dense optical flow algorithm using altera OpenCL SDK
Ulutaş, Umut (201708)FPGA acceleration of computeintensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Dataparallel algorithms have an alternative platform for acceleration, ... 
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
Ulutaş, Umut; Tosun, Mustafa; Levent, Vecdi Emre; Büyükaydın, D.; Akgün, T.; Uğurdağ, Hasan Fatih (Springer International Publishing, 2017)FPGA acceleration of computeintensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Dataparallel algorithms have an alternative platform for acceleration, ... 
FPGA implementation of a low latency and high SFDR direct digital synthesizer for resourceefficient quantumenhanced communication
Annafıanto, Nur Fajar Rızqı; Jabir, M. V.; Burenkov, I. A.; Uğurdağ, Hasan Fatih; Battou, A.; Polyakov, S. V. (IEEE, 202009)A Direct Digital Synthesizer (DDS) generates a sinusoidal signal, which is a significant component of many communication systems using modulation schemes. A CORDIC algorithm offers minimum memory requirements compared to ... 
Generating fast logic circuits for mselect nport round Robin arbitration
Uğurdağ, Hasan Fatih; Temizkan, F.; Gören, S. (IEEE, 2013)This paper generalizes the problem of Round Robin Arbitration (RRA) from 1select to mselect (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ... 
Hardware division by small integer constants
Uğurdağ, Hasan Fatih; Dinechin, F. de; Gener, Y. S. (IEEE, 201712)This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ... 
Hardware implementation of field oriented control for three phase machine drives
Tüfekçi, B.; Önal, B.; Önal, H.; Uğurdağ, Hasan Fatih (IEEE, 20201005)This paper presents a high switching frequency FPGA implementation of Maximum Torque Per Ampere (MTPA) and Flux Weakening which are branch of Field Oriented Control (FOC) method for 3phase machine drives. A common ...
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