Browsing by Author "Temizkan, Fatih"

Now showing 1 - 4 of 4

Metadata only
Fast two-pick n2n round-robin arbiter circuit
(IEEE, 2012-06) Uğurdağ, Hasan Fatih; Temizkan, Fatih; Baskirt, O.; Yuce, B.; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Temizkan, Fatih
A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked requests with (at most) two-hot n-bit output. A round-robin arbiter is fair to its requesters and does this by repeatedly moving its highest priority pointer to the position immediately next to the second requester picked. Presented is the circuit architecture and VLSI implementation of a new scalable two-pick round-robin arbiter with low latency, which is compared with previous work based on logic synthesis results.
Restricted
Multi-pick round robin arbiter
(2012-08) Temizkan, Fatih; Uğurdağ, H. Fatih; Uğurdağ, H. Fatih; Erdem, Tanju; Aktemur, Tankut Barış; Department of Electrical and Electronics Engineering; Temizkan, Fatih
In this thesis, we propose two multi(m)-pick Round Robin Arbiter (RRA) architectures. An m-pick RRA selects the m topmost requests out of n inputs with priority order indicated by an internally kept pointer (with an update policy that ensures fairness among requestors). The architectures that we propose are m-pick Thermo Coded-Parallel Prefix Arbiter (TC-PPA) and Three-Dimensional Programmable m-Selector RRA (3DPmS-RRA). Prior to this thesis, these two architectures existed in the literature as 2-pick and 1-pick arbiters, respectively. Our main contribution to the literature is the generalization of these architectures to m-pick. A logic building block that we call ?Saturated Adder? plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We developed six different variants of 3DPmS-RRA and eight different variants of m-pick TC-PPA. We wrote automated HDL code generators for all variants as well as Cascade Architecture, which is a straight-forward way of implementing a multi-pick RRA using 1-pick Programmable Priority Encoders. Then, all multi-pick architectures were verified and synthesized. Our experimental results show that 3DPmS-RRA architecture is the best choice for all pick sizes (except 2-pick) when timing is the primary design criterion. However, when area is more critical, TC-PPA architecture performs better. It is worthwhile to note that in terms of timing 3DPmS-RRA is better than TC-PPA by a mere 8% at the most based on our synthesis results. However, when we consider area, TC-PPA has significant improvements over 3DPmS-RRA, up to 53%.
Metadata only
RoCoCo: row and column compression for high-performance multiplication on FPGAs
(IEEE, 2011) Uğurdağ, Hasan Fatih; Keskin, O.; Tunç, Cihan; Temizkan, Fatih; Fici, G.; Dedeoğlu, S.; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Tunç, Cihan; Temizkan, Fatih
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.
Metadata only
Synthesis of clock trees for sampled-data analog IC blocks
(IEEE, 2013) Yüce, B.; Korkmaz, S.; Esen, V. B.; Temizkan, Fatih; Tunç, Cihan; Güner, Gökhan; Başkaya, I. F.; Agi, İ.; Dündar, G.; Uğurdağ, Hasan Fatih; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Temizkan, Fatih; Tunç, Cihan; Güner, Gökhan
This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.