Browsing by Author "Dündar, G."

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Distance and power based experimental verification of channel model in visible light communication
(IEEE, 2019) Kısacık, Rıfat; Efe, B. C.; Pusane, A. E.; Uysal, Murat; Baykas, T.; Dündar, G.; Yalcinkaya, A. D.; Electrical & Electronics Engineering; UYSAL, Murat; Kısacık, Rıfat
In this work, a channel model for line-of-sight (LOS) in visible light communication is elaborated. In the proposed channel model, there is no optical component, such as filter or lens, between the transmitting LED and the receiving photodiode. Later, a suitable setup is built for emulation of the mentioned channel model. In the setup, the LED and the photodiode are located in a line-of-sight orientation. The change of the optical power on the photodiode is measured by varying the distance between the LED and photodiode. The measurement result is compared with the channel model. The channel model is in good agreement with the measurement results. Following that, the signal-to-noise ratio (SNR) at the output of the receiver, as a function of the distance, is measured. Measurement results indicate that the SNR value remains below 15 dB after exceeding a distance of 20 cm for the specific LED-Photodiode pair used in the experiment. The optical signal on photodiode drops to the noise level when the distance exceeds 50 cm.
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Fast and efficient circuit topologies for finding the maximum of n k-bit numbers
(IEEE, 2014-08-01) Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G.; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih
Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different (n, k) cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log n + log k), whereas the fastest in the literature is O(log n log k). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.
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Opto-electronic receiver system with post-equalization for visible light communications
(IEEE, 2020-10-05) Kısacık, Rıfat; Erkınacı, T.; Yağan, M. Y.; Pusane, A. E.; Uysal, Murat; Baykaş, T.; Dündar, G.; Yalçınkaya, A. D.; Electrical & Electronics Engineering; UYSAL, Murat; Kısacık, Rıfat
In this work, A significant increase in the data rate is achieved by designing an opto-electronic receiver for the visible light communication system. LEDs used at the transmitter side in the visible light communication system do not allow to transmit high data rates due to limited bandwidth. With the help of an equalizer, the data rate to be transmitted through LED can be increased. The designed opto-electronic receiver includes photodiode, trans-impedance amplifier (TIA), and equalizer blocks. First, the frequency response of the existing LED is extracted and its bandwidth is measured to be around 700 kHz. After obtaining a clear eye opening by transmitting a data at 1 Mbit/s, it is observed that the signal at the receiver side is impaired due to the intersymbol interference when the data rate is 50 Mbit/s. In the established setup, a data rate of 50 Mbit/s is achieved by using the same LED and the signal is properly received at the output of equalizer. Last, the bit error rate is obtained for higher data rates from 50 Mbit/s to 120 Mbit/s. By using only equalizer, a bit error rate of 10 -2 is achieved for the data rate of 90 Mbit/s by using LED with the bandwidth of 700 KHz.
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Synthesis of clock trees for sampled-data analog IC blocks
(IEEE, 2013) Yüce, B.; Korkmaz, S.; Esen, V. B.; Temizkan, Fatih; Tunç, Cihan; Güner, Gökhan; Başkaya, I. F.; Agi, İ.; Dündar, G.; Uğurdağ, Hasan Fatih; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Temizkan, Fatih; Tunç, Cihan; Güner, Gökhan
This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.