Browsing by Author "Akgun, T."

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Rapid design of real-time image fusion on FPGA using HLS and other techniques
(IEEE, 2018) Aydın, Furkan; Uğurdağ, Hasan Fatih; Levent, Vecdi Emre; Güzel, Aydın Emre; Annafianto, Nur Fajar Rızqı; Özkan, M. A.; Akgun, T.; Erbas, C.; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Aydın, Furkan; Levent, Vecdi Emre; Güzel, Aydın Emre; Annafianto, Nur Fajar Rızqı
During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which we developed in a previous design project. Image fusion combines two or more images through a color transformation process. Depending on the application, different fps and/or resolution may be needed. Yet the specifics of the image-processing algorithm may frequently change causing redesign. If the target platform is FPGA, usually rapid yet optimized hardware implementation is required. All these requirements cannot be met only by HLS. Clever approaches in terms of architectural techniques such as unorthodox ways of pipelining, RTL coding, and creative ways of porting interface logic/software allowed us to meet the requirements outlined above. With all these in our arsenal, we were able to get 3 versions of the algorithm (with different fps and/or resolution) running on Cyclone IV and Arria 10 FPGAs in a fairly short amount of time. This paper explains the image fusion algorithm, our hardware architecture as well as our specific flow for rapid implementation of it.
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Tools and techniques for implementation of real-time video processing algorithms
(Springer Nature, 2019-01) Levent, Vecdi Emre; Güzel, Aydın Emre; Tosun, M.; Büyükmıhcı, Mert; Aydın, Furkan; Goren, S.; Erbas, C.; Akgun, T.; Uğurdağ, Hasan Fatih; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Levent, Vecdi Emre; Güzel, Aydın Emre; Büyükmıhcı, Mert; Aydın, Furkan
This paper describes flexible tools and techniques that can be used to efficiently design/generate quite a variety of hardware IP blocks for highly parameterized real-time video processing algorithms. The tools and techniques discussed in the paper include host software, FPGA interface IP (PCIe, USB 3.0, DRAM), high-level synthesis, RTL generation tools, synthesis automation as well as architectural concepts (e.g., nested pipelining), an architectural estimation tool, and verification methodology. The paper also discusses a specific use case to deploy the mentioned tools and techniques for hardware design of an optical flow algorithm. The paper shows that in a fairly short amount of time, we were able to implement 11 versions of the optical flow algorithm running on 3 different FPGAs (from 2 different vendors), while we generated and synthesized several thousand designs for architectural trade-off.
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Using high-level synthesis for rapid design of video processing pipes
(IEEE, 2016) Güzel, Aydin Emre; Levent, Vecdi Emre; Tosun, Mustafa; Özkan, M. Akif; Akgun, T.; Büyükaydın, D.; Erbas, C.; Uğurdağ, Hasan Fatih; Electrical & Electronics Engineering; UĞURDAĞ, Hasan Fatih; Güzel, Aydin Emre; Levent, Vecdi Emre; Tosun, Mustafa; Özkan, M. Akif
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has turned out to be pretty general-purpose except for the ability to handle cyclic inter-iteration dependencies. It also introduces some novel concepts to HLS, such as “pipelined multiplexers”. The synthesis results show that we can achieve better timing or better area results compared to Vivado HLS. Furthermore, the Verilog RTL our HLS tool outputs is much more readable than the one from Vivado HLS. This makes it much easier for the designer to debug and modify the RTL.