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dc.contributor.authorYüce, B.
dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorGören, S.
dc.contributor.authorDündar, G.
dc.date.accessioned2014-12-15T09:20:11Z
dc.date.available2014-12-15T09:20:11Z
dc.date.issued2014-08-01
dc.identifier.issn0018-9340
dc.identifier.urihttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6782653&tag=1
dc.identifier.urihttp://hdl.handle.net/10679/712
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.en_US
dc.description.abstractFinding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different (n, k) cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log n + log k), whereas the fastest in the literature is O(log n log k). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.relation.ispartofIEEE Transactions on Computers
dc.rightsrestrictedAccess
dc.titleFast and efficient circuit topologies for finding the maximum of n k-bit numbersen_US
dc.typeArticleen_US
dc.peerreviewedyesen_US
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.volume63
dc.identifier.issue8
dc.identifier.startpage1868
dc.identifier.endpage1881
dc.identifier.wosWOS:000341523800003
dc.identifier.doi10.1109/TC.2014.2315634
dc.subject.keywordsComputational complexityen_US
dc.subject.keywordsDigital arithmeticen_US
dc.subject.keywordsHardware description languagesen_US
dc.subject.keywordsNetwork topologyen_US
dc.identifier.scopusSCOPUS:2-s2.0-84904811748
dc.contributor.authorMale1


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