Browsing Electrical & Electronics Engineering by Author "(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih"
Now showing items 1-20 of 21
-
25th IFIP/IEEE conference on very large scale integration (VLSI-SoC 2017)
Elfadel, I. A. M.; Uğurdağ, Hasan Fatih (IEEE, 2018-02)The 25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017) was held between 23 and 25 October in the landmark Yas Viceroy Hotel, overlooking the Formula 1 Yas Marina racetrack in Yas Island, Abu Dhabi, ... -
Design and simulation of an optimal energy management strategy for plug-In electric vehicles
Gözüküçük, M. A.; Akdoğan, Taylan; Hussain, Waqas; Tasooji, Tohid Kargar; Şahin, Mert; Çelik, M.; Uğurdağ, Hasan Fatih (IEEE, 2018)Energy management algorithms play a critical role in improving the energy efficiency of modern electric vehicles. In order to be desirable for the customer, electric vehicles should be capable of long distance driving on ... -
Electric vehicle model parameter estimation with combined least squares and gradient descent method
Gözüküçük, Mehmet Ali; Uğurdağ, Hasan Fatih; Dedeköy, Mert; Çelik, Mert; Akdoğan, Taylan (IEEE, 2019)Energy management algorithms have a crucial role in electric vehicles due to their limited driving range. For an energy management algorithm to be effective, we should model the vehicle as accurately as possible. That is, ... -
Experiences on the road from EDA developer to designer to educator
Uğurdağ, Hasan Fatih (IEEE, 2013)This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ... -
Fast and efficient circuit topologies for finding the maximum of n k-bit numbers
Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G. (IEEE, 2014-08-01)Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder ... -
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Kakacak, Ahmet; Guzel, Aydın Emre; Cihangir, Ozan; Gören, S.; Uğurdağ, Hasan Fatih (Elsevier, 2017)We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ... -
Fast parallel prefix logic circuits for n2n round-robin arbitration
Uğurdağ, Hasan Fatih; Baskirt, O. (Elsevier, 2012-08)An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains ... -
Fast two-pick n2n round-robin arbiter circuit
Uğurdağ, Hasan Fatih; Temizkan, Fatih; Baskirt, O.; Yuce, B. (IEEE, 2012-06)A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked ... -
FPGA based DCO-OFDM PHY transceiver for VLC systems
Levent, V. E.; Sağlam, Gürol; Uğurdağ, Hasan Fatih; Annafianto, Nur Fajar Rizqi; Aydın, Furkan; Tesfay, Shewit Weldu; Mohamed, Bassam Aly Abdelrahman; Elamassie, Mohammed; Kebapçı, Burak; Uysal, Murat (IEEE, 2019)Satisfying the demand for high bandwidth and low latency in Visible Light Communication (VLC) systems is a difficult challenge. VLC channels exhibit frequency-selectiveness at peak-speeds. This phenomenon generates a serious ... -
FPGA based particle identification in high energy physics experiments
Uğurdağ, Hasan Fatih; Başaran, A.; Akdogan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)High energy physics experiments require on-the-fly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ... -
Generating fast logic circuits for m-select n-port round Robin arbitration
Uğurdağ, Hasan Fatih; Temizkan, F.; Gören, S. (IEEE, 2013)This paper generalizes the problem of Round Robin Arbitration (RRA) from 1-select to m-select (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ... -
Hardware division by small integer constants
Uğurdağ, Hasan Fatih; Dinechin, F. de; Gener, Y. S. (IEEE, 2017-12)This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ... -
Lossless look-up table compression for hardware implementation of transcendental functions
Gener, Y. S.; Gören, S.; Uğurdağ, Hasan Fatih (IEEE, 2019)Look-Up Table (LUT) implementation of transcendental functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. MultiPartite table method (MP) can circumvent the ... -
Output domain downscaler
Büyükmıhçı, M.; Levent, Vecdi Emre; Guzel, Aydın Emre; Ates, Ozgur; Tosun, Mustafa; Akgün, T.; Erbas, C.; Gören, S.; Uğurdağ, Hasan Fatih (ISCIS 2016: Computer and Information Sciences, 2016)This paper offers an area-efficient video downscaler hardware architecture, which we call Output Domain Downscaler (ODD). ODD is demonstrated through an implementation of the bilinear interpolation method combined with ... -
Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration
Gören, S.; Ozkurt, O.; Yildiz, A.; Uğurdağ, Hasan Fatih; Chakraborty, R. S.; Mukhopadhyay, D. (Elsevier, 2013-02)This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. ... -
Rapid design of real-time image fusion on FPGA using HLS and other techniques
Aydın, Furkan; Uğurdağ, Hasan Fatih; Levent, Vecdi Emre; Güzel, Aydın Emre; Annafianto, Nur Fajar Rızqı; Özkan, M. A.; Akgun, T.; Erbas, C. (IEEE, 2018)During the process of implementing a parameterized hardware IP generator for an image fusion algorithm, we had a chance to test various tools and techniques such as HLS, pipelining, and PCIe logic/software porting, which ... -
RImCom: raster-order image compressor for embedded video applications
Palaz, Okan; Uğurdağ, Hasan Fatih; Ozkurt, O.; Kertmen, B.; Donmez, F. (Springer International Publishing, 2017)This paper presents a real-time, rate controlled, end-to-end (encoder and decoder) hardware solution for memory compression of raster-order video streams—named RImCom (short for Raster-order Image Compression). RImCom ... -
RoCoCo: row and column compression for high-performance multiplication on FPGAs
Uğurdağ, Hasan Fatih; Keskin, O.; Tunç, Cihan; Temizkan, Fatih; Fici, G.; Dedeoğlu, S. (IEEE, 2011)Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are ... -
SOC estimation for li-Ion batteries using extended kalman filter with PID controlled process noise according to the voltage error
Çelik, Mert; Gözüküçük, Mehmet Ali; Akdoğan, Taylan; Uğurdağ, Hasan Fatih (IEEE, 2019)State of Charge (SOC) estimation is critical for battery powered devices in order to find out the remaining charge level. This process is relatively straightforward when the battery is in the resting state. However, it can ... -
Software defined VLC system: implementation and performance evaluation
Hussain, Waqas; Uğurdağ, Hasan Fatih; Uysal, Murat (IEEE, 2015)This paper presents the implementation of an IEEE standard-based Visible Light Communication (VLC) system using software defined radio (SDR) approach. Based on widely used SDR platform Universal Software Radio Peripheral ...
Share this page
