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dc.contributor.authorUğurdağ, Hasan Fatih
dc.contributor.authorKeskin, O.
dc.contributor.authorTunç, Cihan
dc.contributor.authorTemizkan, Fatih
dc.contributor.authorFici, G.
dc.contributor.authorDedeoğlu, S.
dc.date.accessioned2016-02-15T13:38:31Z
dc.date.available2016-02-15T13:38:31Z
dc.date.issued2011
dc.identifier.isbn978-1-4577-1957-8
dc.identifier.urihttp://hdl.handle.net/10679/2350
dc.identifier.urihttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6116419
dc.descriptionDue to copyright restrictions, the access to the full text of this article is only available via subscription.
dc.description.abstractMultiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool.
dc.language.isoengen_US
dc.publisherIEEE
dc.relation.ispartofDesign & Test Symposium (EWDTS), 2011 9th East-West
dc.rightsrestrictedAccess
dc.titleRoCoCo: row and column compression for high-performance multiplication on FPGAsen_US
dc.typeConference paperen_US
dc.peerreviewedyes
dc.publicationstatuspublisheden_US
dc.contributor.departmentÖzyeğin University
dc.contributor.authorID(ORCID 0000-0002-6256-0850 & YÖK ID 118293) Uğurdağ, Fatih
dc.contributor.ozuauthorUğurdağ, Hasan Fatih
dc.identifier.startpage98
dc.identifier.endpage101
dc.identifier.doi10.1109/EWDTS.2011.6116419
dc.subject.keywordsAdders
dc.subject.keywordsApplication specific integrated circuits
dc.subject.keywordsField programmable gate arrays
dc.subject.keywordsIntegrated circuit design
dc.identifier.scopusSCOPUS:2-s2.0-84856094597
dc.contributor.ozugradstudentTunç, Cihan
dc.contributor.ozugradstudentTemizkan, Fatih
dc.contributor.authorMale3
dc.relation.publicationcategoryConference Paper - International - Institutional Academic Staff and Graduate Student


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