Browsing by Author "118293"
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25th IFIP/IEEE conference on very large scale integration (VLSISoC 2017)
Elfadel, I. A. M.; Uğurdağ, Hasan Fatih (IEEE, 201802)The 25th IFIP/IEEE Conference on Very Large Scale Integration (VLSISoC 2017) was held between 23 and 25 October in the landmark Yas Viceroy Hotel, overlooking the Formula 1 Yas Marina racetrack in Yas Island, Abu Dhabi, ... 
An area efficient real time implementation of dual tree complex wavelet transform in field programmable gate arrays
Canbay, F.; Levent, V. E.; Serbes, G.; Uğurdağ, Hasan Fatih; Goren, S.; Aydin, N. (IEEE, 2015)Biomedical signals (BSs), which give information about the normal condition and also the inherent irregularities of our body, are expected to have nonstationary character due to the timevarying behavior of physiological ... 
Combined AES + AEGIS architectures for high performance and lightweight security applications
Şahin, F.; Uğurdağ, Hasan Fatih; Yalçın, T. (Springer International Publishing, 2014)AES has been the prominent block cipher since its introduction as the standard. It has been the cipher used in almost all new applications that require solid, unbreakable security with reasonable resource usage. Several ... 
Costbenefit approach to degradation of electrolytic capacitors
Kirişken, B.; Uğurdağ, Hasan Fatih (IEEE, 2014)Aluminum electrolytic capacitors are widely used as a filter or bulky capacitor after rectification stages of switching power supplies (SMPS). Flyback, forward, and resonant converter topologies, which are widely used in ... 
Darbe i̇şaretleri̇ i̇çi̇n aşırıhızlı FPGA tabanlı eǧri̇ beti̇mlenmesi̇
Başaran, A.; Uğurdağ, Hasan Fatih; Akdoğan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)Bu çalışmada anlatılan donanım 1.5 GHz AnalogSayısal Çevirici’den gelen darbe işaret dizisini işleyebilmekte ve darbe işaretlerini genlik, yükselme/düşme süresi ve varış zamanı parametreleriyle özetleyebilmektedir. Söz ... 
Defectaware nanocrossbar logic mapping through matrix canonization using twodimensional radix sort
Gören, S.; Uğurdağ, Hasan Fatih; Palaz, O. (ACM, 201108)Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuckopen/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is ... 
Enabling differencebased dynamic partial self reconfiguration for large differences
Gören, S.; Özkurt, Ö.; Türk, Y.; Yıldız, A.; Uğurdağ, Hasan Fatih (IEEE, 2013)This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration ... 
Experiences on the road from EDA developer to designer to educator
Uğurdağ, Hasan Fatih (IEEE, 2013)This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic ... 
Fast and efficient circuit topologies for finding the maximum of n kbit numbers
Yüce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dündar, G. (IEEE, 20140801)Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with kbits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximumfinder ... 
A fast circuit topology for finding the maximum of n kbit numbers
Yuce, B.; Uğurdağ, Hasan Fatih; Gören, S.; Dundar, G. (IEEE, 2013)Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (lowlatency) ... 
Fast multiplier generator for FPGAs with LUT based partial product generation and column/row compression
Kakacak, A.; Guzel, A. E.; Cihangir, O.; Gören, S.; Uğurdağ, Hasan Fatih (Elsevier, 2017)We present a new parallel integer multiplier generator for FPGAs. It combines (i) a new Generalized Parallel Counter (GPC) grouping algorithm for column compression with (ii) a LUT based partial product generation, is (iii) ... 
Fast one and twopick fixedpriority selection and muxing circuits
Tosun, Mustafa; Özkan, M. Akif; Güzel, Aydin Emre; Uğurdağ, Hasan Fatih (IEEE, 2016)Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with ... 
Fast parallel prefix logic circuits for n2n roundrobin arbitration
Uğurdağ, Hasan Fatih; Baskirt, O. (Elsevier, 201208)An n2n roundrobin arbiter (RRA) searches its n inputs for a 1, starting from the highestpriority input. It picks the first 1 and outputs its index in onehot encoding. RRA aims to be fair to its inputs and maintains ... 
Fast twopick n2n roundrobin arbiter circuit
Uğurdağ, Hasan Fatih; Temizkan, F.; Baskirt, O.; Yuce, B. (IEEE, 201206)A regular (onepick) roundrobin arbiter circuit picks one active requester (if any) out of n requesters. A twopick roundrobin arbiter selects up to two requesters. An n2n twopick roundrobin arbiter indicates the picked ... 
FPGA based particle identification in high energy physics experiments
Uğurdağ, Hasan Fatih; Başaran, A.; Akdogan, T.; Güney, V. U.; Gören, S. (IEEE, 2012)High energy physics experiments require onthefly processing of signals from many particle detectors. Such signals contain a high and fluctuating rate of pulses. Pulse shape hints particle type, and the amplitude relates ... 
FPGA bitstream protection with PUFs, obfuscation, and multiboot
Gören, S.; Özkurt, Ö.; Yıldız, A.; Uğurdağ, Hasan Fatih (IEEE, 2011)With the combination of PUFs, obfuscation, and multiboot, we are able to do the equivalent of partial bitstream encryption on lowcost FPGAs, which is only featured on highend FPGAs. Lowcost FPGAs do not even have ... 
FPGA implementation of a dense optical flow algorithm using altera openCL SDK
Ulutaş, Umut; Tosun, Mustafa; Levent, Vecdi Emre; Büyükaydın, D.; Akgün, T.; Uğurdağ, Hasan Fatih (Springer International Publishing, 2017)FPGA acceleration of computeintensive algorithms is usually not regarded feasible because of the long Verilog or VHDL RTL design efforts they require. Dataparallel algorithms have an alternative platform for acceleration, ... 
Generating fast logic circuits for mselect nport round Robin arbitration
Uğurdağ, Hasan Fatih; Temizkan, F.; Gören, S. (IEEE, 2013)This paper generalizes the problem of Round Robin Arbitration (RRA) from 1select to mselect (mRRA) and offers new circuit architectures for it. RRAs are found in networking equipment and computer systems with high ... 
Hardware division by small integer constants
Uğurdağ, Hasan Fatih; Dinechin, F. de; Gener, Y. S. (IEEE, 201712)This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an ... 
An indepth look at prior art in fast roundrobin arbiter circuits
Uğurdağ, Hasan Fatih; Baskirt, O. (Özyeğin University, 08.01.2011)Arbiters are found where shared resources exist such as busses, switching fabrics, processing elements. Roundrobin is a fair arbitration method, where requestors get nearequal shares of a common resource or service. ...
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